This invention concerns a semiconductor memory integrated circuit, in particular a MOS 1Tr/1C (1 transistor/1 capacitor) semiconductor memory integrated circuit, and a method of its manufacture.
FIG. 3 is a sectional diagram of the steps in the conventional process used to manufacture a MOS 1Tr/1C semiconductor memory integrated circuit. In the figure, the cell area is shown on the left and the peripheral transistor area on the right.
As shown by the figures, in the conventional manufacturing process, a SiN/SiO.sub.2 laminated film 2 is deposited as a selective oxidation mask on a silicon substrate 1 (FIG. 3A).
The laminated film 2 is etched to form openings 4 at such parts of the substrate 1 where isolation oxide areas 3 (referred to hereafter as field areas) are to be formed (FIG. 3B). Impurities are ion implanted to form channel stops of a fairly high concentration and of the same conductivity type as substrate 1 (FIG. 3B) and an isolation oxide film 5 is then formed in the field area 3 by thermally oxidizing laminated film 2 as a mask.
After removing laminated film 2, a dielectric layer 6 and a capacitor electrode, for example a polysilicon layer 7, are formed in turn in a cell capacitor area of substrate 1 so as to form a cell capacitor 8, and this capacitor is then covered with an insulating film 9 (FIG. 3D).
A cell transfer transistor 10 and a peripheral transistor 11 are then formed in the cell transfer transistor area and peripheral transistor area of substrate 1, as follows. This can be achieved in the following manner. First, a gate of the polyside structure is made by forming, on substrate 1, a gate insulating film 12, a conducting polysilicon layer 13, and a metal silicide layer 14. This gate is used as a mask to form, in substrate 1, diffusion layer 15 of impurities of fairly high concentration and of opposite conductivity type to substrate 1, and side walls of insulating material 16 are formed on the wall of the gate. Then, using the side walls 16 and the gate as a mask, a diffusion layer 17 of impurities of high concentration and opposite conductivity type to subs&rate 1, is formed in substrate 1. Thus transistors 10, 11 of the LDD (Lightly Doped Drain) structures are formed (FIGS. 3E, F).
When transistors 10 and 11 have been formed, an insulating layer 18 is formed over the entire surface of substrate 1, and contact holes 19 are opened in order to make contact between the diffusion layers 15 of the transistors and a metalization layer that will be later formed (FIG. 3F).
Finally, a metallization layer 20 which is in contact with the diffusion layers 15 of the transistors 10, 11 through the contact holes 19 is formed on insulating layer 18, and a passivation film 21 is deposited on this to give the final structure (FIG. 3G).
In the above method, however, as the cell capacitor 8 formed on the surface of substrate 1 is planar, it is impossible to avoid a large loss of capacitance when surface areas are reduced and densities are increased, and moreover, as capacitor is formed between the cell capacitor electrode and substrate 1, soft errors due to .alpha. rays and other radiation were a problem.